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. A computer uses a memory unit with 256k words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers, and an address part. a) How many bits are there in the operation code, the register code part, and the address part? b) Draw the instruction word format and indicate the number of bits in each pant c) How many bits are there in the data and address inputs of the memory? 2. The following control inputs are active in the bus system. For each case, speify the S, SS Load of Memor adde register transfer that will be executed during the next clock transition Register a 1 1 1 IR b11o PC c. 1 0 0 DR Read Write 000АС Add 3. The following register transfers are to be executed in the system. For each transfer, specify: (1) the binary value that must be applied to bus select inputs S, S, and S;(2) the register whose LD control input must be active (if anyl: (3) a memory read or write operation (if needed); and (4) the operation in the adder and logic circuit (if any) a) AR PC b) IR+ MIAR] c) M[AR]←TR. d) AC DR, DR AC (done simultaneously). 4. Consider the instruction formats of the basic computer and the list of instructions as studied previously. For each of the following 16-bit instructions, give the equivalent four-digit hexadecimal code and explain in your own words what it is that the instruction is going to perform. a) 0001 0000 0010 0100 b) 1011 0001 0010 0100 c) 0111 0000 0010 0000 Show transcribed image text . A computer uses a memory unit with 256k words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers, and an address part. a) How many bits are there in the operation code, the register code part, and the address part? b) Draw the instruction word format and indicate the number of bits in each pant c) How many bits are there in the data and address inputs of the memory? 2. The following control inputs are active in the bus system. For each case, speify the S, SS Load of Memor adde register transfer that will be executed during the next clock transition Register a 1 1 1 IR b11o PC c. 1 0 0 DR Read Write 000АС Add 3. The following register transfers are to be executed in the system. For each transfer, specify: (1) the binary value that must be applied to bus select inputs S, S, and S;(2) the register whose LD control input must be active (if anyl: (3) a memory read or write operation (if needed); and (4) the operation in the adder and logic circuit (if any) a) AR PC b) IR+ MIAR] c) M[AR]←TR. d) AC DR, DR AC (done simultaneously). 4. Consider the instruction formats of the basic computer and the list of instructions as studied previously. For each of the following 16-bit instructions, give the equivalent four-digit hexadecimal code and explain in your own words what it is that the instruction is going to perform. a) 0001 0000 0010 0100 b) 1011 0001 0010 0100 c) 0111 0000 0010 0000
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Note: The first question is done as per Cheggguidelines, please repost others.
A memory in which 256k words of each 32-bit
there are four parts in the instruction
1) Indirect bit
2) Operation bit
3) A register code
4) Address
There are 256k words are in there
which means 262144
each word is 2^32
No of registers are= 64
a)
Number of bits in the operation code
total number of registers= 2^6
in the code part number of registers are = 6
in the address part
256*1024= 2^18
no pf bits in operand code= total no of bits = no of address part -no of bits in register code -1
= 32-18-6-1
= 7
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A memory in which 256k words of each 32-bit there are four parts in the instruction 1) Indirect bit 2) Operation bit 3) A register code 4) Address There are 256k words are in there which means 262144 each word is 2^32 No of registers are= 64 a) Number of bits in the operation code total number of registers= 2^6 in the code part number of registers are = 6 in the address part 256 times 1024= 2^18 no pf bits in operand code= total no of bits = no of address part – no of bits in register code -1 = 32 – 18 – 6 – 1 = 7 The format is Address bits are 18 from 0 to 17 Register code contains 6 bits 18 to 23 operation code contains 7 bits 24 to 30 Indirect bit is: i.e 31^st bit No. of bits in data & address i/p of memory
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